Abstract: We present a 40 Gb/s asynchronous self-routing network and node architecture that exploits bit
and packet level optical signal processing to perform synchronization, forwarding and
switching. Opticalpackets are self-routed on a hop-by-hop basis through the network by using
stacked optical tags, each representing a specific optical node. Each tag contains control signals
for configuring the switching matrix and forwarding each packet to the appropriate outgoing
link and onto the next hop. Physical layer simulations are performed, modeling each optical subsystem
of the node showing acceptable signal quality and Bit Error Rates. Resource reservationbased
signaling algorithms are theoretically modeled for the control plane capable of providing
high performance in terms of blocking probability and holding time.
Abstract: We demonstrate an all-optical clock and data recovery
circuit for short asynchronous data packets at 10-Gb/s line
rate. The technique employs a Fabry–P{\'e}rot filter and an ultrafast
nonlinear interferometer (UNI) to generate the local packet
clock, followed by a second UNI gate to act as decision element,
performing a logical AND operation between the extracted clocks
and the incoming data packets. The circuit can handle short
packets arriving at time intervals as short as 1.5 ns and arbitrary
phase alignment.
Abstract: We present optical clock and data recovery for 10 Gb/s asynchronouspackets. The original data are
sampled with an optical gate powered by clock packet, generated with a novel packet clock recovery circuit.
Abstract: In this paper, we demonstrate optical transparency
in packet formatting and network traffic offered by all-optical
switching devices. Exploiting the bitwise processing capabilities
of these “optical transistors,” simple optical circuits are designed
verifying the independency to packet length, synchronization
and packet-to-packet power fluctuations. Devices with these attributes
are key elements for achieving network flexibility, fine
granularity and efficient bandwidth-on-demand use. To this end, a
header/payload separation circuit operating with IP-like packets,
a clock and data recovery circuit handling asynchronouspackets
and a burst-mode receiver for bursty traffic are presented. These
network subsystems can find application in future high capacity
data-centric photonic packet switched networks.
